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ADVANCED SIMULATION

Signal Integrity &
HyperLynx Design

Master high-speed interfaces, DDRx, and SerDes simulation using Mentor Graphics HyperLynx. Validate 25Gbps links before fabrication.

25Gbps Simulation
IBIS-AMI Models

Course Modules

1. Fundamentals of SI
  • Transmission line theory & termination
  • Reflections, Overshoot, and Undershoot
  • Understanding Jitter and Timing budgets
  • Invoking HyperLynx & Schematic entry
  • Introduction to IBIS Models
2. Crosstalk & Reflections
  • Topology analysis for reflection minimization
  • Crosstalk analysis strategies (NEXT/FEXT)
  • Managing PCB effects on signal quality
  • On-chip termination techniques
3. Memory & Power
  • DDR3/DDR4 Design & Simulation
  • Eye Diagram analysis for memory interfaces
  • FPGA Power Supply design challenges
  • Thermal aspects of high-speed boards
4. Advanced High-Speed (SerDes)
  • High-Speed SerDes Transceivers (25Gbps+)
  • S-Parameters for high-speed apps
  • Pre-layout & Post-layout with IBIS-AMI
  • TX & RX Equalization techniques

Hands-on Labs

Lab 1: Modify IBIS models & define PCB stackup.
Lab 2: Reflection Analysis & Termination strategies.
Lab 3: Crosstalk Analysis & minimization.
Lab 4: DDR3/4 Simulation with Eye Diagrams.
Lab 6: Pre-layout simulation with IBIS-AMI (~25Gbps).
Lab 7: Post-layout simulation verification.
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